All-digital phase-locked loops (ADPLLs) are replacing traditional charge-pump PLLs (CP-PLLs) in an increasing number of electronic systems. ADPLLs contain more nonlinear analog components and digital delta-sigma modulators (DDSMs) than their CP-PLL counterparts. The soft and hard nonlinearities associated with the analog components and DDSMs, respectively, produce distinct families of spurious tones (spurs) and additional noise, both of which are undesirable in applications. This book explains why ADPLLs are, at first glance, inherently worse than CPPLLs in terms of their spur and noise performance. It then describes a set of innovative mitigation techniques that can be used to make ADPLLs perform as well as, or even better than, CP-PLLs. Readers will understand both qualitatively and quantitatively how spurs are produced in ADPLLs. They will learn how to distinguish between spurs that result from soft and hard nonlinearities and will become familiar with state of the art methods to minimize the production of jitter and spurs and see many examples of the methods in practice.